After a hardware reset and unless specific steps are taken to set it up, a Cyrix 6x86 CPU will identify itself as an unknown type 486. This 'feature' was chosen by Cyrix in order to avoid potential compatibility problems with legacy software that would eventually misidentify a Cyrix CPU as an Intel Pentium and fail to execute some specific Intel Pentium instructions. Note that this problem does not exist on Linux/gcc systems, since gcc (up until version 2.7.2.3 at least) does not make use of any Intel Pentium specific instructions.
Most recent Intel 486 CPUs and all Intel Pentium CPUs correctly execute the CPUID instruction (see specific Intel Application Note).
Cyrix/IBM 6x86(L) CPUs are setup so that after a hardware reset, the CPUID instruction is disabled (this is not the case for the 6x86MX), and specific steps have to be taken in order to enable its execution. Moreover, a complete identification of the 6x86, 6x86L and 6x86MX CPUs will involve different steps from those needed by Intel processors.
Enabling the CPUID instruction during boot time will allow the Linux kernel to identify a Cyrix CPU in /proc/cpuinfo:
| processor cpu model vendor_id stepping fdiv_bug hlt_bug fpu fpu_exception cpuid wp flags bogomips |
: 0 : 586 : Pentium 75+ : CyrixInstead : unknown : no : no : yes : yes : yes : yes : fpu de cx8 : 133.12 |
Notice the kernel did not identify the model (speed), revision and stepping of my Cyrix/IBM 6x86L PR166+ CPU. Just enabling the CPUID instruction is not enough, a more sophisticated CPU identification patch is needed. If we apply my latest short Cyrix patch, we get this:
| processor cpu model vendor_id stepping fdiv_bug hlt_bug sep_bug fpu fpu_exception cpuid level wp flags bogomips |
: 0 : 586 : 6x86L : CyrixInstead : 4.2 : no : no : no : yes : yes : 1 : yes : fpu de cx8 : 133.12 |
Now, the IBM 6x86L has been correctly identified (revision 4.2, see Rev. column in table below).
CPUs are marked in a very precise way that makes identification of CPU revision and rating possible. For example, the following is a 6x86L-PR150+ manufactured and sold by IBM:
I know this is a purely aesthetic detail and that once the CPU case is closed we don't get a chance to look at the chip again, but those IBM-manufactured CPUs have a pleasant quality look. The golden dot and the cut angle both indicate the correct orientation of the CPU (pin 1).
Another example of interesting case marking is the following AMD K6-166:
Recently I have heard rumours of grey-market K6 CPUs being remarked. Well, AMD seems to have taken this very seriously: all recent K6 CPUs have their clock rating laser-etched in the top right corner. Here is an enlarged view of the etched characters, which are just 1mm high:
There have been three 6x86 generations or models: the original 6x86, the split voltage 6x86L and now the 6x86MX. The original 6x86 design is sometimes called M1, and the new 6x86MX, M2. These were codenames in the development phase.
The original 6x86 went through several revisions (Rev. 2.4, Rev. 2.5, Rev. 2.6), and one optical shrinking (from Rev. 2.7 to Rev. 3.7). It was then redesigned for a split-voltage, 0.35µm technology, resulting in the 6x86L and paving the way for the new 6x86MX.
The 6x86MX is a redesign of the 6x86 architecture, with a few (but significative) architectural enhancements. Its main advantage over the 6x86 is a much larger L1 cache (64Kb vs. 16Kb in the 6x86 and 6x86L) and the availability of higher clock rates. Sure, there are also those two MX letters that remind us of the fact that it will also execute MMX instructions, but right now GNU/Linux does not make use of the MMX instruction set.
The next step for Cyrix, now under the banner of National Semiconductor, will be a 0.25µm 6x86MX (or MXi) with higher core clock rates, which could reach 300 MHz. We will have to wait until 1998 to see whether or not National Semiconductor is serious about using the 6x86MX as its flagship processor.
The MXi is an improved 6x86MX with much higher floating-point performance. Cyrix has not released much information about his new chip yet, so I assume it's still in its design/simulation stages.
Almost all Cyrix/IBM 6x86 family chips have been manufactured by IBM up to now, with some batches by SGS-Thomson. We can expect some 6x86MXi 0.25 micron CPUs will be manufactured by IBM, but in the long term production could be switched over to National Semiconductor fabs (and technology).
The following table summarizes the 6x86 CPU family history:
| Model | Rev. | Vcc | Max. Clock | DIR0 | DIR1 | Notes |
| 6x86 | 2.4 | 3.3V* | 2 x 66 MHz | 3xh | 14h | VSPM implementation problematic. L1 cache bug ? |
| 6x86 | 2.5 | 3.3V* | 2 x 66 MHz | 3xh | 15h | VSPM implementation problematic. L1 cache bug ? |
| 6x86 | 2.6 | 3.3V* | 2 x 66 MHz | 3xh | 16h | VSPM implementation problematic. L1 cache bug ? |
| 6x86 | 2.7 | 3.3V* | 2 x 66 MHz | 3xh | 17h | VSPM OK. L1 cache OK. |
| 6x86 | 3.7 | 3.3V* | 2 x 75 MHz | 3xh | 17h | Same mask as 2.7, but lower power consumption due to optical scaling. |
| 6x86L | 4.2 | I/O: 3.3V
Core: 2.8V |
2 x 75 MHz | 3xh | 22h | Split rail voltage supply. A single new instruction (64-bit compare and exchange) and one new register (CCR4). |
| 6x86MX | 1.3 | I/O: 3.3V
Core: 2.9V |
3 x 66 MHz | 5xh | 03h | No VSPM. MMX compatible, large (64Kb) L1 cache, many new features. CPUID instruction identifies the chip as an A step PPro. |
| 6x86MX | 1.4 | I/O: 3.3V
Core: 2.9V |
3.5 x 75 MHz | 5xh | 04h | This revision supports higher clock rates than Rev. 1.3. |
| * Note: for revisions 2.4 to 3.7, some ICs were shipped with single Vcc of 3.3V, whereas others were shipped with dual Vcc, 3.3V I/O and 3.52V core. The only way to tell is by checking the markings on the CPUs. The chips themselves are the same, they were probably tested at 3.3V, and when the yield was considered unacceptable, retested at 3.3V + 3.52V. | ||||||
Last updated on January 5, 1998.
Copyright 1997 Andrew D. Balsa